Omega navigation receiver station pair selection and lop display system

ABSTRACT

In an Omega navigation receiver, a system for providing four station phase comparison using a single time-shared phase difference detector and providing flexibility in the selection of Omega stations for phase differencing.

United States Patent Zitzow I76] lnvemor: Harold Zitzow Oak Assistant ExaminerRichard E. Berger Reading, Mass. 01867 {221 Filed: June 1,1973

[2i 1 Appl. NO; 366,045 57] ABSTRACT 52] U.S. Cl.v 343/105 R; 324/83 FE In an Omega navigation receiver, a system for provid- Sl l Int. Cl. Gills 1/30 ing four station phase comparison using a single time- (SBI Field 0fSearch...343/l()5 R; 324/83 FE, 83 FM shared phase difference detector and providing flexibility in the selection of Omega stations for phase dif- [56] References Cited ferencing.

UNITED STATES PATENTS 3.440.535 4/1969 Thornhill 324/83 FM 7 Claims, 11 Drawing Figures OMEGA NAVIGATION RECEIVER 3.689.925 9/1972 STATION PAIR SELECTION AND LOP DISPLAY SYSTEM I Primary Examiner-Maynard R. Wilbur UP/DN EARLY LATE OPPOSITE 0A0 EDGE 0 DET L LOOP SQ.

LIM

COUPLER 54 OPPOSITE EDGE O DET l3 .6 KHZ HL onset/w 10.2 KHZ r56 KHZ TRACK OlSPLAY DRIVE a COUNTER lO.2 HZ

LOOP CLOCKS TIMING CONTROL OISP SEQ CONTROL B STN SEQ SEL SW SLEW SYNC

STNS 8 RANGE 20-26 July 22, 1975 Hulland 343/105 R OMEGA NAVIGATION RECEIVER STATION PAIR SELECTION AND LOP DISPLAY SYSTEM FIELD OF THE INVENTION This invention relates to Omega navigation receivers and in particular to a system for selecting and displaying particular lines-of-position.

BACKGROUND OF THE INVENTION The Omega navigation system will ultimately employ eight stations all transmitting. in timed sequence, phase-locked signals which may be phase differenced at the receiver to provide. for any single pair of stations, a phase difference and a corresponding line of position within a lane of 8 or more miles. Accordingly, in order to provide two intersecting lines of position which would establish a "fix" within a lane, at least three stations must be received and tracked so that the phase difference between two different pairs may be monitored to track a vessel's position as well as change of position. Three pairs of stations are, however, desirable and it is preferable that four be used for safety margins. Even with such a reduced number over the total available for the eight Omega stations, great timing complexity results in permitting a receiver operator to select any one or more of the possible four pairs for immediate display and to conveniently select any four stations in any order from the eight available stations to generate the pairs. The requirements of keeping track of when each station selected is received, where that station is tracked for maintaining information on its received phase, and where the phase difference information is stored for display by the operation at will, can thus immensely complicate receiver design and put it economically beyond the reach of fleet or individual vessel operators.

BRIEF SUMMARY OF THE INVENTION In accordance with the preferred embodiment of the present invention for an Omega navigation receiver, an overall system concept of minimized complexity is employed and includes a plurality of tracking loops which are assigned to track each respective Omega station signal desired, by front panel control, and including a single phase difference detector which is automatically switched to any or all of the tracking loops of the selected station pairs to instantaneously detect phase difference and display the corresponding line-of-position data at that given time.

In particular, the receiver of the present invention provides for the reception of four Omega stations at both [02 KH and 13.6 KH, so that ultimately 24 and S-mile lanes may be provided in the LOP format. The receiver is structured so that the operator may select any four stations for tracking and any four of the at least six possible paired combinations of those four stations for phase differencing. The receiver is caused to track all eight transmissions (both frequencies), and with all eight transmissions being accurately tracked, a single phase differencing system is provided which may be selectively switched amongst the different pairs as well as lane width combinations at any instant to provide a complete LOP for that station pair within an 8 or 24-mile lane. Adjustment of the LOPs for vessel movement across lanes is automatically maintained by the tracking loops.

BRIEF DESCRIPTION OF THE DRAWINGS These and other features of the present invention will be fully set out below in the solely exemplary detailed description of the preferred embodiment and in the accompanying drawings of which:

FIG. 1 is a presentation of the Omega receiver front panel;

FIG. 2 is a block diagram of the overall receiver;

FIG. 3 is a signal waveform diagram useful in explaining the operation of a portion of the receiver for phase detection;

FIG. 4 is a more detailed presentation of the front end portion of the receiver;

FIG. 5 is a detailed presentation of the phase detection portion of the receiver;

FIG. 6 is a detailed description of the oscillator of the receiver and associated frequency division components;

FIG. 7 is a detailed description of the tracking loop section of the receiver;

FIG. 8 is a detailed presentation of the timing and control portion of the receiver;

FIG. 9 is a detailed presentation of the display sequence control portion of the receiver;

FIG. 10 is a detailed presentation of the display driver portion of the receiver; and

FIG. 11 is complete elemental implementation of the display sequence controller.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A full understanding of the operation and construction of an Omega navigation receiver according to the present invention may be obtained by reference to FIGS. 1-3 for a general overview of receiver operation, and FIGS. 4-12 for a complete view of receiver structure.

In FIG. I, the receiver front panel is presented and affords a view of system features. At the top, digital displays 12, l4, l6 and 18 indicate LOP and synchronization information. Two digit display 12 indicates the two Omega stations for which an LOP is presented in the three digit lane display 14, and percent of distance between lanes shown in display 16. The two stations selected for phase difference representation are determined by switches 20, 22, 24, and 26 which select either 8 or 24-mile lanes for phase indication for a twostation pair selected in a corresponding pair of selector switches in the eight switch panel 28.

Initial synchronization of receiver timing to the received sequence of eight Omega stations (A-l-l) is achieved from use of the sync switch 30 and slew control 32. Switch 30 is depressed until the station in digit 18 is the selected station for synchronization (usually the strongest). Slew switch 32 is used to bring receiver timing and station transmission time as close as possible.

The lane set switches 34 and 36 permit fast or slow slewing of the lane LOP shown in digits 14 to the lane nearest the known location for at least three of the four two station pairs selected via switches 28. Omega phase maps for the location of the receiver are used for this purpose.

Actual receiver operation can now be viewed by reference to the general block diagram of FIG. 2 and the waveform diagram of FIG. 3. In FIG. 2, the l0.2 KH,

and the 13.6 KH Omega transmissions are gathered by an antenna 40, matched to a line 42 by a coupler 44 which conveys them to an amplifier 46 within the receiver. 102 KH and 13.6 KH filters 48 and 50, respectively, separate the two frequencies. A noise gate 52 blocks the signal from filter 48 in the absence of proper signals. Amplifiers 54 and 56 boost the outputs of filters 48 and 50 and respectively apply them to hard limiters 58 and 60 to provide hard limited 10.2 KH, and 13.6 KH signals. [t is a feature of this receiver that the hard limiting need not be so accurately performed as to prevent asymmetries in the hard limited squarewave because the respective phase detectors 62 and 64 operate to detect peak signal points independent of squarewave symmetry. A field strength indicator 66 provides a measure of relative Omega station signal strength to facilitate synchronization.

The features of the phase detectors 62 and 64 which provide accurate phase detection may be understood by reference to FIG. 3 showing rising and falling edges of a typical hard limited 10.2 KH signal waveform 68 separated by several cycles and rising and falling edges of a 81.6 H tracking loop squarewave signal 70 from one of four l0.2 KH tracking loop counters 72, 74, 76 and 78, for the corresponding station. The phase detector, 62 in this case, provides an indication of whether opposite, falling and rising, edges of the received, hard limited signal occur early or late with respect to the lower frequency loop squarewave representative of loop synchronization with the corresponding received signal. The lower frequency provides sampling every 125th edge of the received signal to limit the effect of filter ringing. An odd harmonic is selected to insure rising and falling edge correspondence between received and loop signals. An early/late output signal is provided from the phase detector 62 for each edge of signal 70 to a corresponding one of four variable counters 80, 82, 84 and 86 to adjust the pulse rate provided by the appropriate counter to the corresponding tracking loop counter thereby to adjust its synchronization. An electronic multiplexer 88 selects the appropriate loop counter squarewave for application to the phase detector 62 and electronic switch 90 directs the early/late signal to the appropriate variable counter 80-86. Multiplexer 88 and switch 90 are controlled by a timing and control system 92 which is synchronized to the received station sequence using the synch and slew switches.

lt is apparent that if the received squarewave has perfect symmetry this system for phase synchronization will produce accurate synchronization of each tracking loop to the corresponding received signal. If, however, the received signal is asymmetrical, the tracking loops will synchronize to the received limited signal such that the early and late signals from rising edge comparisons equal the late and early signals, respectively, for the falling edge comparisons. This will occur in the noise free case of asymmetry at any point where the detected rising and falling edges of the received signal span zero or an even number of edges in the loop signal 70 creating a phasing indeterminancy.

However, this ideal asymmetry does not occur in the real world, where noise variation in symmetry (a form of random width modulation) occurs on the real received signals. A typical distribution for the rising and falling edges in the presence of noise is shown in H6. 3. As long as the noise variation in rising and falling edges exceeds the variations in these edges due to asymmetry produced by the signal limiter (as shown in FIG. 3), a significant percent of the time, the average phasing of the tracking loops will be synchronized to the average phasing of the received signals. The 8L6 H edges will intercept the distribution curve at the same point and the 81.6 H squarewave will be centered in all cases. The effects of both noise and asymmetry are then cancelled. As will be seen from the description below, the manner in which the tracking loops are synchronized insure an averaging of these effects.

It is apparent that by keying the early/late pulses to opposite edges of the received and hard limited signal, the effect of asymmetry in the limited signal is cancelled and in effect the peak point of the received cycles are detected.

For the purpose of tracking the 13.6 KH hard limited signal, a similar tracking loop is employed using the output of the opposite edge phase detector 64, switch 94 and four sequentially selected variable count counters 96, 98, 100, 102, which in turn clock 13.6 KH tracking loop counters 104, 106, 108 and 110. A multiplexer 112 directs the detection signal from the appropriate tracking loop counter 104-110 to the phase detector 64.

Slewing of the tracking loop counters 72, 74, 76, 78, 104, 106, 108 and 110 to the correct phase lane is achieved by the lane set controls through the display sequence controller 114. The switches 20-26 also operate through the display sequence controller 114 to operate the display drive and counter system 116 to select the appropriate two counters in the set 72-78 for display of the 8-mile lane phase difference in displays 12, 14 and 16 of display 118. A signal digital differencer in system 116 provides a count corresponding to the phase difference between the selected 10.2 [(1-1, loop counters for display in display 118. Where 24-mile lanes are employed, because of estimated position uncertainties, system 116 operates to effectively provide a digital difference corresponding to the phase difference of the difference frequency for the Omega 10.2 Kl-l and 13.6 Kl-l, stations.

The timing and control system 92 provides overall system timing control by effectively assigning a loop counter and variable rate counter to each of the first four stations selected by switches 28. The last four selections must accordingly be taken from among the first four. All eight station selections control system 92 to gate appropriate counter pulses to phase detection and display elements.

The detailed implementation for this system may now be understood from the remaining figures. In FIG. 4, the RF front end" of the receiver is shown and in cludes from antenna 40, a coupling transformer with spark gap 132 for lightning protection. Antenna 40 drives a balanced line 134 and in turn a receiver transformer 136 having limiting diodes 138. An FET input stage 140 provides a high input impedance matching to amplifiers 142 and 142' for the 10.2 KH, and 13.6 KH, signal paths. The amplifier 142 is adjusted for peak gain at 10.2 KH, and its output is applied through resistor 146 and capacitor 148 to a 10.2 Kl-l crystal filter 150. A noise limiter 152 across resistor 146 and capacitor 148 detects preset noise levels and diverts the signal during their occurrence. The output of filter is buffered by an ampifier 154 and applied to a 50 db gain, hard limiter 156 having a positive feedback path 158 to provide amplitude symmetry adjustment. A balanced output of the limiter is applied to a line receiver 160 having a feedback path 162 for higher level amplitude symmetry. The output of the line receiver 162 provides the 10.2 KH HL (hard limited) signal.

The signal path for the 13.6 KH signal is the same except for frequency differences and the absence of the noise limiter. The corresponding components of the 13.6 KH path are designated by primes.

The 10.2 KH output of the hard limiter 156 is mixed in mixer 164 with an internally generated KH signal to provide 200 I-I,,. A low-pass filter 166 passes the 200 H to a phase-locked loop 168 for detection to provide an output signal representing coherent signal detection to an indicator 170.

The 10.2 KH, and 13.6 KH HL signals are applied to the phase detector circuitry of FIG. 5. For simplicity, only the 10.2 KH signal path is shown, an identical circuit being used for 13.6 KH except for the differences attributable to frequency. In FIG. 5, the 10.2 KH HL signal is applied to an exclusive OR gate 180 along with a tracking loop squarewave signal having a lower frequency squarewave in order to provide the operation illustrated and described above with respect to FIG. 3. The output signal from gate 180 will accordingly be an indication of early or late timing of the received Omega phase with respect to the internally generated phase represented by the selected tracking loop squarewave signal. The output of gate 180 is applied to a flip-flop 182 for storage and its outputs, which set the condition for advance and retard signals, are applied to divide-by- 16 counter 184 which is loaded to the mid-count by a start commutator signal at the beginning of each station transmission segment. The counter 184 is clocked through a delay circuit 186 by the 10.2 KH, second delay signal, the delay providing sufficient time for the signals to pass through to the counter in the normal processing. The last three bits from the counter 184 are decoded by a decoder circuit 188 to provide an indication of extreme counter states. The counter and decoder 184 and 188 thereby provide a digital filter to minimize the effect of small variations in the advanceretard signals. The all ones condition from the decoder 188 is applied to a NAND gate 190 along with the delayed clock from the delay circuit 186. The output of the NAND circuit 190 is applied to the clear input of a flip-flop 192. The clock input of flip-flop 192 is provided from a multiplexer 194, which receives the 10.2 KH sample select signal described below to select the appropriate one of the particular station counter outputs described below. The output of the flip-flop 192 will accordingly be a first state when the phase detector detects normal phasing and in the second state when the phasing is either early or late. The output of flipflop 192 is applied to a NAND gate 196 which has on a further input the output of the flip-flop 182. The output of NAND gate 196 is in one state for early or normal condition and the opposite for late phasing condition. It is applied to a dual decoder 198 for application to a selected one of counters 200, 202, 204 and 206 to preload them to predetermined counts. The particular one of the counters 200-206 preloaded is selected by the same 10.2 KH sample signals applied to multiplexer 194. The decoder 198 functions as a switch to direct the output of the NAND gate 196 to the appropriate counter preload input. The opposite state output of flip-flop 192 is also applied to the dual decoder 198. The two outputs from the decoder 198 to the counters 200-206 provide a preload of an eleven when normal phasing is detected to result in a divide-by-S condition. When timing is detected as advanced, a ten is pre loaded into the appropriate counter causing a divideby-6 which retards the tracking loop, and where the timing is detected as retarded a twelve is preloaded in the counter to result in a divide-by-4 and an advance of the tracking loop. Each output of the counters 200206 is applied to the multiplexer 194 for selection of the appropriate 10.2 KH signal for clocking the flipflop 192. The 13.6 KH circuits operate functionally in the same manner as that of the 10.2 KH circuits.

It is to be noted that the circuitry described above provides an adjustment in a counting sequence provided at the output of the counters 200-206 which will be used to adjust the phase of the tracking loop counters described below. As a result of the particular techniques of detecting the phase relationship between a locally generated standard and the opposite edge transitions of the received Omega signals as explained above, the effect of asymmetry in the hard-limiting circuitry is eliminated. The counters 200206 are clocked at 5.1 MH the 13.6 KH path counters at 6.8 MH

The remaining circuitry of FIG. 5 is provided for the purpose of controlling the oscillator of the Omega receiver. For this purpose, the TC output of the counter 184 is applied through a divide-by-16 counter 208 to a preset jumper wire system to a divide-by-16 counter 210 in tandem with a second divide-by-l6 counter system 212. A preset jumper wire module 214 between counters 208 and 210 is preset to provide one of the possible division states by counter 208 depending upon the voltage-to-frequency characteristics of the oscilla tor employed in the Omega receiver. The counters 210 and 212 are up-down counters and the up-down state is controlled by the output of the flip-flop 182 depending upon whether the detection is early or late. The counters 210 and 212 will thereby integrate the early or late phase error and provide a digital signal representative thereof to a digital-to-analog converter 216, the analog output of which is applied through an amplifier 218 to the VCO control input of the crystal voltage controlled oscillator 220 shown in FIG. 6. The amplifier 218 has an integration characteristic to provide additional filtering.

With regard to FIG. 6, the voltage controlled oscillator 220 and associated frequency division circuitry is shown. The oscillator 220 is adjusted to have a 102 MH output. The output of the oscillator 220 after appropriate signal buffering to prevent effects from loading is applied through a divide-by-12 circuit 222. The divide-by-2 bit output is ANDed with the output of the oscillator 220 in a gate 224 to provide a 5.1 MH output signal for the counters 200-206 in FIG. 5. A rate multiplier technique is employed with the divide-by-l2 counter 222 to provide a 6.8 MH signal for similar counters in the 13.6 KH phase detector 64 shown in the block diagram of FIG. 2. For this purpose, two bits of the counter 222 are NANDed in a gate 226. The output of the NAND gate 226 is applied to an NOR gate 228 and its output is applied to a NAND gate 230. Other inputs to the gates 228 and 230 are respectively from the first bit of the divider 222 and from the output of the oscillator 220.

The output of the NAND gate 226 is applied as a clock input through a chain of two divide-by-16 counters 232 and 234 which are connected to provide a 10 KH clock output and a 10 KH squarewave used elsewhere in the system.

The tracking loops are shown in FIG. 7 and consist of eight counter-divider chains, four for the 10.2 Kl-l signal processing and four for the 13.6 Kl-l, signal processing. In FIG. 7, one of each of the two different frequency signal processing tracking loop chains is illustrated, the other three for each frequency being identical. Each counter chain in the FIG. 7 circuitry tracks the respective four 10.2 KH, and 13.6 KH stations transmissions selected by the front panel controls.

For the 10.2 KH signal, each counter chain comprises a divide-by-50 counter 240 with its output applied to the CET input of a binary counter 242 which in turn has its TC output applied to the CET input of a decade counter 244. The TC output of the counter 244 is applied to the CET input of binary counter 246. The counter 240 is clocked by the 1.02 MH output of the corresponding one of the counters 200-206 in FIG. 5. The counters 242 and 244 are connected together to provide a divide-by-l25 count and counter 246 provides a divide-by-l6 count. The counters 242 and 244 operate to provide the divide-byJZS function employing a parallel enable input to the counters 242 and 244 in response to the final output from counter 244 to set a divide-by-13 condition in counter 242 in the first cycle of that counter. The counter 244 is enabled for a divide-by-S. The total cycle count will be divide-by- 125 (one 13 and 7 sixteens).

The counter 242 which adjusts the count function from a divide-by-l25 to a divide-by-l27 or divide-by- 123, depending upon whether the lane is being changed up or down. Odd harmonics are used as explained above. A specific signal is applied to the counter 242 for this purpose by the display sequence controller discussed below in response to setting of the lane set front panel controls to either up or down and fast or slow set condition.

The output of a counter 244 is applied to one of a set of four inputs of a dual multiplexer 248 and its output is applied to an AND gate 250 along with the 10.2 KH enable signals described below. Its output is applied through an OR gate 252 to a flip-flop 254 and serially to a second flip-flop 256. The signal from the output of flip-flop 254 provides the first 10.2 KB, delay pulse and second flip-flop 256 provides the second delay pulse. The 00 output of the counter 246 is applied to the first of a second set of four inputs of the dual multiplexer 248 and its output provides the 81.6 H squarewave output signal applied to the exclusive OR gate 180. The multiplexer 248 receives similar signals on the remaining of each of the two sets of three signals from the other counter chains to select the appropriate counter chain for providing the outputs to the gate 250 and as the 81.6 H squarewave output of the loop in response to the 10.2 KH sample select signal applied to the multiplexer 248.

The output of the counter 246 at the TC terminal is applied to an AND gate 262 along with the output of an inverter 258 which receives the TC output of the counter 244 after an inverter 260. The inverter 260 provides the parallel enable signal for the counters 242 and 244. The output of the AND gate 262 is applied on one of four inputs to a dual multiplexer 264 and its output provides the start-stop signal for the 10.2 Kl'l= signals.

The 13.6 Kl-I tracking loops are also represented in FIG. 7 in detail for one counter chain of the four. The 13.6 KH, loops are similar except that no lane set function is required since the 13.6 Klrl signals are from the same stations and are used for differencing with the 10.2 KH, signals to provide a 24-mile lane where vessel position is not known with sufficient accuracy to permit use of the S-mile lane. The 13.6 KH loop includes a divide-by-50 counter 270, the TC output which is applied to a tandem connection of counters 272 and 274 to provide a divide-by-250 function. The TC output of the counter 272 is applied through an inverter 276 to the parallel enable input to provide the divide-by-250 function, essentially two cycles of the divide-by-12S function associated with the 10.2 KH tracking loop. The inverted output (TC) of the counter 272 is again inverted by inverter 278 and applied as one input of an AND gate 280. The AND gate 280 receives on a second input the detected 8 and 16 count of the second counter 274 detected through an AND gate 282 from the three last significant outputs thereof. The AND gate 280 detects a divide-by-l25 function of counter 272 and 274 and its output is applied to the first of a second set of four inputs of the multiplexer 264. Its output provides a 13.6 KI-I start-stop signal. The multiplexer 264 is activated by a display start-stop select signal, to be described below, for selection of the appro priate one of each of the two sets of four inputs.

The TC output of the counter 274 is applied to the first of four inputs of a dual multiplexer 284 and the divide-by-Z output is applied to the first of a second set of four selectable inputs of the dual multiplexer 284. The first output of the multiplexer is applied to an AND gate 286 with the 13.6 KH enable signal and its output applied to a chain of flip-flops 288 and 290 which provide respective outputs for the first and second 13.6 KH, delay pulses. The second output of the multiplexer 284 provides the 108.8 I-I squarewave loop signals for use in the 13.6 KH phase detector.

With respect to the timingand control function of the Omega receivers specifically as represented by the timing and control system 92, display sequence controller 114 and display drive and counter 116 in the FIG. 2 block diagram, this circuitry is shown in detail in FIGS. 8-10. With respect to FIG. 8 in particular, the timing and control system 92 is shown in detail. The purpose of the FIG. 8 timing and control logic is to provide timing output signals in response to selected station sequencing from the switches 28 in FIG. 2 so that the appropriate tracking loops are enabled at the corresponding time in the repeating sequence of time slots for the Omega station transmissions, as well as providing other activation signals for use throughout the Omega receiver. For this purpose, a counter chain composed of binary counters 300, 302, 304, 306 and 308 are provided and are clocked by the 10 KH signal applied to the first counter 300 in the chain. The chain of counter 300-308 establishes sequencing in the Omega station transmission cycle and various outputs are taken from the counter chain to be used throughout the system as will be explained below. Counter 304 cycles once each interval between transmissions by each station. Counter 306 cycles during transmission and counter 308 defines the station transmission sequence. The chain of counters 300-308 is manually set to the sequence of the received stations using the sync and slew switches 30 and 32 on the panel. For this purpose, the sync signal is applied through an AND gate 310 to the CEP input to the binary counter 306. The other input of the AND gate 310 is from the output of the last counter 308. The last three states of the output of the last counter 308 provide a set of signals defined as the NEXT 13.6 signal (a binary code for the next l3.6 KH station in the eight station sequence) and these are also applied to a decoder 312 which provides sequential activation of eight independent signal lines which define the commutation sequence (COM/SEQ), one for each station. These eight signal lines are also applied to and OR network 314 which has one output defining the NEXT 10.2 signal (a three bit binary code for the NEXT 10.2 Kl-l station to transmit) as well as two outputs representing the existence of the B, C, D, F and B, D, E, H signals in the eight sequence commutation lines. This output is ANDed with the Q0 output from the counter 308 in the AND network 316 and applied to the first and second preload inputs, respectively. of the counter 306.

The function of the above circuitry is to cause the counters 300-308 to synchronize to a selected station when the sync switch 30 is depressed in conjunction with the display of the selected station designation in display 18 from the commutation sequence by display logic described below. Such operation will cause the counter 306 to stop counting. The sync switch is then released at the end of the display of signal reception in indicator 170 for that same station. The station selected for synchronization is usually the strongest in the area and thus easily identified in indicator 170. More accurate synchronization is achieved through the use of the slew switch 32 and the respective advance and retard signals provided by it. These are applied to set and reset inputs of flip-flop 320, and to inputs of an OR gate 322. The output of this OR gate is applied to the J input of a flip-flop 324 and its Q output is applied to the K input thereof as well as one input of an AND gate 326. The other input of the AND gate 326 is taken from the 0 output of the flip-flop 320. The output of the AND gate 326 is applied to the higher order preload inputs of the counter 304 and through an inverter 328 to low order preload inputs. The TC output of the counter 304 is appplied through an inverter 330 to the preload enable input of the same counter. The net result of this circuitry is to permit advancing or retarding of the counter chain 300-308 by changing the preload conditions in the counter 304 in response to the advanced or retarded position of the slew switch 32. This function permits more accurate synchronization of the chain of counters 200-308 to the transmission sequence through manual observation of displays 18 and 170.

The TC output of the counter 306 as well as the 00 output of the counter 308 are ANDed in a gate 332 to provide at the output thereof the START COM signal used elsewhere in the circuitry. With the appropriate sequence of station transmissions now determined by the chain of counters 300-308, it is possible to activate appropriate portions of the Omega receiver at the time of reception of the station selected by the switch system 28. These switches are eight in number for selecting the two stations to be phase difierenced in each of four possible phase differencing sequences which the receiver is capable of. Each of the eight switches has 3 bits associated with it which may be in either of two states. There is a unique three bit code for each station selected by each switch. The first, second and third bits for each of the eight switches are applied as eight inputs to respective multiplexers 336, 338 and 340 in the FIG. 8 timing system. The multiplexers 336-340 are sequenced to select all the eight switch inputs in response to the output of the counter 304 during the interval between station transmissions. The outputs of each of the multiplexers 336-340 (a three bit code for each station to which a switch is set) are applied to an exclusive OR network 342 for the 10.2 KH, signal path and to an exclusive OR network 344 for the 13.6 Kl-l signal path. In addition, the OR network 342 receives the NEXT 10.2 signal and the OR network 344 receives the NEXT 13.6 signal. The three outputs from each network 342 and 344 are applied to respective AND gates 346 and 348. Each output to an AND gate 346 or 348 represents the condition of exclusive ORing the output of corresponding multiplexers 336-340 with the corresponding one of the three lines in the NEXT 10.2 signal or NEXT 13.6 signal and thus activation of all three outputs indicates that the multiplexers 336-340 have an output code (station) agreeing with the next station transmission at 10.2 and l3.6 KH, The AND gates 346 and 348 also receive the inverted 00 output of the counter 308 indicating a commutation interval (between stations). First and second three bit storage registers 350 and 352 for the 10.2 KH and l 3.6 KH signal paths, respectively, are provided in order to store a code indication of the next station to transmit, if it has been selected by the switches 28. The J input of the first storage flip-flop in each register is loaded with the respective output of AND gates 346 or 348 and will accordingly indicate whether the succeeding station is one identified by the switch system 28 for use in phase measurement. The remaining two flip-flops in the three bit registers 350 and 352 have their 1 inputs provided from the Q1 and Q2 outputs of the counter 304, then defining a two bit code for the one first four states in the eight state counter 304 sequence corresponding to the switch which is set to the next station to transmit. The registers 350 and 352 are reset by the output of an AND gate 354 which receives the 00 output and TC outputs of the counters 308 and 306 respectively. The three outputs of each flip-flop in each of the three bit registers 350 and 352 are applied to respective AND networks 356 and 358 where they are ANDed with the Q0 commutator signal output from the counter 308. The 10.2 sample enable and 13.6 sample enable signals are provided from the AND networks 356 and 358 in response to the first flip-flop in each of the registers 350 and 352 as ANDed by the respective gates in the networks 356 and 358 to indicate that a selected station is coming in the defined interval. The last two flipflops in each of the registers 350 and 352 are applied to the AND network 356 and 358 to provide the 10.2 sample select and 13.6 sample select signals for use by the multiplexers 248 and 284 in FIG. 7, as well as elsewhere in the system. These thus define which of switches 28 and 20-26 correspond to the next station. The outputs in the last two flip-flops in the register 350 are also provided to an eight bit latch circuit 360, each flip-flop being directed to four alternate latches. Each latch is clocked by one of four outputs of an AND network 362 which responds to the Q0, Q1 and Q2 outputs of the counter 304 to select its last four states as well as Q1 and O2 outputs of the counter 302 and the commutator signal from the counter 308. The AND network 362 identifies the last four states of counter 304 and for each state loads a pair of corresponding latch circuits with the station code of the first four states when the same station was selected. Accordingly the latch 360 will store a code for the last four switch selections in system 18, thereby to identify the corresponding tracking loop. The output of each of the eight storage elements in the latch 360 is applied to a multiplexer 364 which is activated by a display switch selection input to provide four first and second outputs as a display command for the display sequence controller to be described below, enabling it to select the correct tracking loop.

In addition, the first, second and third bits for each of the eight switches in the system 28 are applied to the eight inputs of multiplexers 366, 368 and 370 in FIG. 8. The outputs of these multiplexers provide the alpha character display controls used in the display driver and are controlled by an LOP SEQ identification signal from the display sequence controller to be described below.

With reference to FIG. 9, the detailed circuitry implementation of the display sequence control function will be described. The function of the display sequence controller is to respond to the selection of an 8 or 24 mile lane request and LOP station identifications from range switches -26 to provide display control signals which insure that the display and associated counter are gated to the appropriate tracking loops for appropriate intervals. The display sequence controller of FIG. 9 also operates to gate the l0.2 KH, and the 13.6 KH start-stop signals under control of the stations identified for each LOP and the range selection switches to appropriate 1.02 MH and L36 Ml-I, COUNT ENABLE control lines for the display counter of FIG. 10. For this purpose, the four signals from the four switches 20-26 indicating 8 mile lane position selection for each of the four station pairs selected in the switching network 28 are applied through OR gates 38] to four inputs of a multiplexer 380. The similar four switches from the 24-mile lane contacts of the switches 20-26 are applied to a further set of four inputs of the multiplexer 380 as well as through the OR gates 38]. The multiplexer 380 is controlled by the Q2 and O3 outputs of a four bit binary counter 382 and provides four outputs which respectively are designated 8+24 and not 8+24, and 24 and not 24 for the appropriate switch conditions. The 24-mile lane signals as well as the outputs of the OR gates 381 are applied to a logic network 384 which provides an output signal indicating that one switch and only one switch has been selected and is used by the lane set logic described below. The counter 382 is controlled by the 00, NEXT 13.6 signal which is applied to it for clearing and is advanced by the output of an OR network 386 which receives both the l0.2 KH start-stop and the 13.6 KH, start-stop signals. The output of network 386 is provided as either the 10.2 or 13.6 start-stop signal in response to the states of the counter 382 applied to it as well as the outputs of the multiplexer 380 applied to it. This output advances the counter 382 and is applied to a gating network 388 which is also controlled by the counter 382 and multiplexer 380. The gating network 388 provides a display clear signal as well as loading corresponding flip-flops 390 and 392 from which the L02 MH and L36 MH count enable signals are respectively taken.

The effect of the networks 386 and 388 in conjunction with the counter 382 and multiplexer 380 is to set the flip-flop 390 to begin the l.02 MH counting in the display counter of FIG. 10 with the 10.2 KHZ start signal for the appropriate station and to stop it with the l0.2 KHZ stop signal. Typically the start signal will be provided from multiplexer 264 in FIG. 7 for one station in a pair and the stop signal from the other station in the pair. The flip-flop 392 is similarly controlled with the 13.6 KHZ start-stop signal where a 24-mile lane designation has been shown through the switches 20-26. This results in the operation of the counter of FIG. 10 to provide in the case of 8 mile lanes a count up at LOZMH, during the interval between the startstop signals of the two tracking loops whose difference in timing is measured for the corresponding LOP and for 24 mile lanes a countdown at 1.02MB then up at 1.36 MH for the interval between start-stop signals in the corresponding 13.6KH, tracking loops.

Additional signals provided by the display sequence control systemof FIG. 9 include the LOP SEQ signals provided from the O2 and O3 outputs of the counter 382 as well as the display switch selector signals and display start-stop select signals which are provided from a logic system 392 in response to the output states of counter 382 by the logic configuration shown in the diagram. The up-down control for the counter of FIG. 10 is provided as the output of an and gate 394 which receives the NOT 24 signal from multiplexer 380 as well as a signal from gate net work 388 to identify the shift from 1.02 to 1.36 MH counting.

The lane set controls at the bottom of FIG. 9 respond to the fast and slow and up and down signals from the lane set switches 34 and 36 to provide the down and normal signals as applied to the tracking loops in FIG. 7. For this purpose the up and down signals are applied to a flip-flop 395 which has one output to an and gate 396. The second output to the and gate 396 is provided from the O output of a flip-flop 398. The 6 output of flip-flop 398 as well as the output of and gate 396 are applied to a switching network 400 controlled by the display start-stop select signal to route the two signnals to each of a corresponding one of two sets of four outputs described below. The fast and slow signals are applied through a clock logic system 402 along with a 102 H lane set signal, the lane set enable signals and a five PPS signal which is ANDed with the next 13.6 Oosignal and provided from a flip-flop 404 for the different rate lane set pulses applied to the switch 400.

A set of Orgates 406 responds to the outputs of the switch 400 in pairs. The first two Ored pairs providing the first and third phase selector signal, the second and fourth phase being provided from those respective signals ANDed in gates 407 with the first line of the LOP SEQ signal. The first and third phase and second and fourth phase signals for the normal lane set control are provided in similar manner from the outputs of the second pair of ORgates 406 and second pair of and gates 407. This defines the outputs of the display sequence controller.

The final element of the receiver, the display driver and the single display counter are shown in FIG. 10. A multiplexer 410 receives on first and second sets of four inputs the 1.02 MH signals for the four difi'erent stations selected from the 10.2 KH channel counters of FIG. and the L36 Ml-l phase B signals for these stations from the corresponding 13.6 KH channel counters. The multiplexer 410 is also responsive to the 1.36 MH, enable signal for selecting between the two signal paths. The output of the multiplexer 410 is applied to the clock input of a chain of five decade counters 412, 414, 416, 418 and 420. The signal from multiplexer 410 is applied through an OR gate 422 which receives the output of an OR gate 424 that ORs the L36 Ml-l count enable and [.02 MH count enable signals. Since the gate 422 is an OR function and 424 is an OR function on the enable signals, a path in the output of multiplexer 410 is provided when one of the enable signals is present. The counters 412-420 are cleared by the display clear signal from FIG. 9 and are controlled for up or down counting by the up-down control signal also from FlG. 9 for counting up at 1.02 MH for 8 mile lanes and counting down at L02 followed by counting up at 1.36 MH for 24 mile lanes. The display start-stop select defines which station loop to select.

Each of the decade counters 412-420 has a BCD- seven segments decoder 426 attached to its output and in turn each decoder 426 drives a corresponding sevensegment display for the percent of lane deviation in the last two digits 16 as well as the LOP lane in the most significant three digits 14.

For driving the first and second alpha numeric displays 12 as well as the synchronization display 18 alpha numeric drivers are provided as well. The first alpha designation in the display 12 is driven by the first, third and fifth LSE outputs of the alpha display from FIG. 8 through a decoding network 430 having typically logic as shown to provide five outputs for designating the eight alpha characters used of Omega station identification. A similar logic sequence 432 responds to the LSE 2, 4, and 6 signals from HO. 8 to activate the corresponding second display element of the display 12 to designate the second of the stations selected for the phase difference and corresponding LOP. The output display for the sequence of display characters is driven by the COM/SEQ signals through further logic 434, as shown, to provide the output signals for driving the display 18.

This ends the complete detailed description of the Omega receiver. However, for further clarity in understanding the specific construction of the elements employed for the display sequence controller of FIG. 9, a FIG. 11 is included as a specific, detail element by element implementation of the corresponding circuitry. Each of the logic networks is fully implemented and is positioned in the same corresponding portion of the drawing as in FIG. 9.

Having above described a full detailed system for providing a Omega navigation receiver according to the invention it will occur to those skilled in the art than other combinations or alternatives may be practiced within the spirit of the invention. Accordingly it is intended to limit the scope of the invention only as indicated in the following claims.

What is claimed is: 1. 1n a navigation receiver, a system for providing tracking of a selectable plurality of Omega station broadcasts and determination of phase differences between a plurality of the selected station broadcasts comprising:

means for receiving the sequence of Omega station broadcasts on at least one frequency thereof;

means for providing operator selection of a plurality of Omega stations which is less than the total in said sequence of broadcasts, the selection being by pairs of said stations;

a plurality of tracking loops for maintaining phase synchronization with received broadcasts;

means for phase synchronizing said tracking loops to said received broadcasts;

means responsive to operator station selection for identifying a separate tracking loop for synchronization to each different, selected station;

single means for detecting the phase difference between two tracking loops; and

means responsive to each station pair selection for sequentially providing phase difference detection of each selected pair by said detecting means.

2. The system of claim 1, further including a display for providing output indications of the detected phase differences.

3. The system of claim 1 further including means for adjusting said tracking loops to provide phasing changes therein corresponding to one or more whole cycle changes in synchronization with said received broadcasts thereby to change LOP lanes corresponding to detected phase differences.

4. The system of claim 1 wherein said detecting means includes a counter and means for causing said counter to count at a first rate in an interval defined by the time between predetermined phase points of said tracking loops.

5. The system of claim 4 wherein:

said receiving means is responsive to at least two frequencies of Omega station broadcasts; and

means are provided to control said counter to count in opposite directions at different rates for plural intervals defined by the time between predetermined phase points of the tracking loops for plural corresponding frequencies thereby to provide a phase difference representing larger lane widths.

6. The system of claim 1 wherein said means for providing operator selection includes:

eight switches grouped in four groups of two switches to identify four station pairs from among four stations to be tracked.

7. The system of claim 6 further including:

a display; and

means for selecting one of the switch groups and corresponding pair line of position lane width for display on said display of a detected phase difference between the stations in the selected group.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION PATENT NO. 1 3, 896,443

DATED 1 July 22, 1975 INVENTOR(S) Harold P. Zitzow It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below;

Cover Page Assignee corporation not listed on printed patent Epsco, Incorporated, Westwood, Mass. 02090 Column 11, line 49, "not 8 24" should read --NOT 8 24--.

Column 11, line 49, "not 24" should read NOT 2 Column 11, line 70, "390 and 392" should read -390 or 392--.

Column 12, line 44, "signnals" should read signals--.

Signed and Scaled this thirteenth Day of April1976 [SEAL] A ttest:

RUTH C. M AHSON C. MARSHALL DANN Alresrmg Ojjrver Commissioner of Parents and Trademarks 

1. In a navigation receiver, a system for providing tracking of a selectable plurality of Omega station broadcasts and determination of phase differences between a plurality of the selected station broadcasts comprising: means for receiving the sequence of Omega station broadcasts on at least one frequency thereof; means for providing operator selection of a plurality of Omega stations which is less than the total in said sequence of broadcasts, the selection being by pairs of said stations; a plurality of tracking loops for maintaining phase synchronization with received broadcAsts; means for phase synchronizing said tracking loops to said received broadcasts; means responsive to operator station selection for identifying a separate tracking loop for synchronization to each different, selected station; single means for detecting the phase difference between two tracking loops; and means responsive to each station pair selection for sequentially providing phase difference detection of each selected pair by said detecting means.
 2. The system of claim 1, further including a display for providing output indications of the detected phase differences.
 3. The system of claim 1 further including means for adjusting said tracking loops to provide phasing changes therein corresponding to one or more whole cycle changes in synchronization with said received broadcasts thereby to change LOP lanes corresponding to detected phase differences.
 4. The system of claim 1 wherein said detecting means includes a counter and means for causing said counter to count at a first rate in an interval defined by the time between predetermined phase points of said tracking loops.
 5. The system of claim 4 wherein: said receiving means is responsive to at least two frequencies of Omega station broadcasts; and means are provided to control said counter to count in opposite directions at different rates for plural intervals defined by the time between predetermined phase points of the tracking loops for plural corresponding frequencies thereby to provide a phase difference representing larger lane widths.
 6. The system of claim 1 wherein said means for providing operator selection includes: eight switches grouped in four groups of two switches to identify four station pairs from among four stations to be tracked.
 7. The system of claim 6 further including: a display; and means for selecting one of the switch groups and corresponding pair line of position lane width for display on said display of a detected phase difference between the stations in the selected group. 